Gate Drive Circuits
Technical Lecture Session
Gate Drive Circuits I
Resonant gate driver, Time-segmented methodology, SIC, High frequency
A novel time-segmented methodology is proposed to analysis the impacts of resonant gate on both driver loss saving and power transistor switching characteristics. Current studies on RGD are quite general and the nonlinear feature brought by MOSFET miller capacitor was ignored, which leaded to un-optimized resonant inductor selection and poor understanding in RGD influence on MOSFET switching behaviors. In this design, driving intervals are divided into segments. Non-linear feature of miller capacitor is firstly included. A FB series resonant gate driver for SiC is built. It achieves up to 43% driving loss reduction and 75% reduction in switching speed.